Increment enumeration type in VHDL

Question

In vhdl I can define my own enumeration type and create a signal of this type:

type tp is (red,green,blue,yellow);
signal sg: tp := red;

But now I want a for loop to run over all of these states. Something like

for i in sg'min to sg'max loop
   <something>
end loop;

In c++ there are iterators for this purpose. But in VHDL all I can find is sg'pos that converts the signal to a number that I can increment. But I cannot seem to find a way to convert the number back to a signal.

Answer 1

This is what you need:

for i in tp'left to tp'right loop
   <something>
end loop;

`left and `right are called type attributes. They are useful in your testbench, but not recommended for your design. This is because you the synthesiser may change the order of the enumerations, which might cause you problems.