How are interrupts handled on SMP?

Question

How are interrupts handled on SMP (Symmeteric multiprocessor/multicore) machines? Is there only one memory management unit or more?

Say two threads, A and B running on different cores touch a memory page (at the same time) which is not there in the page table, in which case there will be a page fault and a new page is brought in from the memory.

What is the sequence of events which will happen? If there is one memory management unit, to which core is the page fault forwarded to? How does the kernel handle it? Are there multiple instances of the kernel, each one running on a different core? If so, how do they synchronize on such events as page fault handling?

Answer 1

Well, it depends on the specific architecture, but from what I can remember from the Intel docs...

There are two main sources of interrupts:

• Internal: These are generated by the CPU itself. Includes faults, traps, software interrupts, etc.
• External: These are hardware interrupts generated by peripherals.

The internal interrupts are always delivered to the CPU that generated it. The external ones are sent to an arbirary core.

In modern models, interrupts can also be delivered using a bus-like system instead the old interrupt driven one, but I ignore if this model is being used in any current OS.

About the MMU, each core has its own, of course, but they are usually forced the same segments by the OS, so they can be used symmetrically. Note that most of the mapping between physical and virtual memory are actually in memory, and that is always shared.

About the sequence in your example:

• The page fault is forwarded to the core that generated it.
• The kernel updates its MMU tables, that are protected by a shared lock or similar.
• No, there is only one kernel, usually, unless you apply a model of virtualization.
• They synchronize using a shared lock or similar structure. If both cores happen to fault at the same page at the same time... well it's not a big deal, actually.

Answer 2

On multicore/multiprocessor architectures, an APIC is used to route interrupts to cores/processors. As the name implies, APICs can be programmed to do the routing as desired.

Regarding the synchronization of the kernel: This depends on the kernel/OS. You can either use a scheme with locking (although IPIs might be necessary on non-cachecoherent architectures) or you can also use your suggested approach of running a kernel on every core and use some kind of explicit inter-kernel communication.

Barrelfish is an example of an OS running multiple kernels. If you are interested in that kind of architecture, you might want to read the paper "The Multikernel: A new OS architecture for scalable multicore systems"