Does RISC-V mandate two's complement or one's complement signedness, or is it implementation-determined?

Question

I have looked through the ISA spec and searched the internet for the answer to this, but I could not find it.

In the RISC-V ISA, should negative numbers be represented with one's complement or two's complement? Or, is this decision left to implementors?

The reason I ask is that I am writing an RV32I simulator, and this would affect how I store negative numbers in the simulated memory, for example.

Answer 1

The RISC-V architecture requires twos-complement integer arithmetic. This can be most directly seen from the fact that it specifies a single addition instruction, not a pair of signed and unsigned addition instructions. In twos-complement arithmetic, signed and unsigned addition are the same operation; in ones-complement (and sign-magnitude) they are not the same.

It appears to me, skimming the architecture manual, that the authors considered the choice of twos-complement integer arithmetic too obvious to bother mentioning. There hasn't been a CPU manufactured in at least 25 years that used anything else.