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Looking from this intel core i7 nehalem microarchitecure
It seems that each core has it's own private Register file. So I have a couple of short questions, because I thought that there is only 1 set of registers not dependent on number of cores.
I know the questions are highly microarchitecture dependent but I think majority of modern x64 intel cpu's follow the same design principle.
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Commonly, each core of a multi-core CPU can have its own clock, but an unneeded core may have its clock shut down to reduce energy consumption. Of course, with those multiple cores, there has to be yet another bus to connect the cores on a CPU, and that too has a clock.
Because x86-64 evolved from a 32-bit ISA which in turn evolved from a 16-bit ISA, each GPR has a set of subregisters that hold the lower 8, 16 and 32 bits of the full 64-bit register. So that's 16 full-width GPRs, fanning out to another 52 subregisters. Registers in this group: 68.
A CPU can contain one or more processing units. Each unit is called a core. A core contains an ALU , control unit and registers .
Each core has its own set of registers, MMU, TLB, level 1 caches (data and instruction), level 2 cache (this depends on processor) etc. Cache Coherency is supported across cores via "QPI" and in the case of high end Core 7 and server-based processors like Xeon, Cache Coherency is supported across processors on a multi-processor mother board by exposing "QPI" on the external pins of those processors (for processors where multi-processor cache coherency is not supported, "QPI" is not "exposed").
Wiki article: Nehalem
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Yes, each core has its set of registers. "Core" is equivalent of separate CPU on socket but with "multicore" the electronic wiring is simple.
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