Can someone explain the process of multi-precision multiplication in assembly?

Question

Refer to the figure below and this link.

Regarding Figure 2.3, I understand why M (multiplier) and N (multiplicand) are in those orders that are listed in "Partial product..M..L" that's in the rightmost column. It comes from how we were normally taught to multiply:

I understand why the figure is 64-bits long, because it's 32-bits times 32-bits.

I understand the addresses go from P~P+7 that way because the H.O. bit of the final product starts at P and L.O. bit of the final product ends at P+7.

I understand why each large rectangle is split into an upper and lower half, because the HCS12 can only handle a maximum of 16-bits times 16-bits at a time.

My problem: The way each small rectangle (lower and upper halves) are arranged is confusing me. Apparently, it's supposed to mimic the simplified multiplication process, which I can understand how is being done. I just don't understand entirely how it translates into the figure. The link from my first line also shows a similar process. I don't want to guess or assume what I think is happening. Can someone please explain in large detail (preferably steps) how you figure out which small rectangle goes into which column and row; or in other words, can you tell me how the multiplication process translates into the figure?

Answer 1

The equation you have is

( M_H<<16 + M_L ) x ( N_H<<16 + N_L )

with << meaning "shift left by". Note that a shift left by 16 is equivalent to a multiplication by 65536, and two shifts by 16 are equivalent to one by 32.

If you multiply this out, you get

M_L x N_L +
M_H<<16 x N_L +
M_L x N_H<<16 +
M_H<<16 x N_H<<16

If you pull the shifts out:

(M_L x N_L) << 0 +
(M_H x N_L) << 16 +
(M_L x N_H) << 16 +
(M_H x N_H) << 32

Now the shift amounts show the number of bits each block is shifted by left in the graphic.